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IDT71V67603S166BQG Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V67603S166BQG Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  SEPTEMBER 2004 DSC-5310/06 1 ©2004 Integrated Device Technology, Inc. Features x x x x x 256K x 36, 512K x 18 memory configurations x x x x x Supports high system speed: – 166MHz 3.5ns clock access time – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time x x x x x LBO LBO LBO LBO LBO input selects interleaved or linear burst mode x x x x x Self-timed write cycle with global write control ( GW GW GW GW GW), byte write enable ( BWE BWE BWE BWE BWE), and byte writes (BW BW BW BW BWx) x x x x x 3.3V core power supply x x x x x Power down controlled by ZZ input x x x x x 3.3V I/O supply (VDDQ) x x x x x Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V67603/7803 are high-speed SRAMs organized as 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect IDT71V67603 IDT71V67803 256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67603/7803 can provide four cycles of dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operationisselected( ADV=LOW),thesubsequentthreecyclesofoutput data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100- pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). A0-A18 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4(1) Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5310 tbl 01 Pin Description Summary NOTE: 1. BW3 and BW4 are not applicable for the IDT71V67802. |
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