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FS6128-06 Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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FS6128-06 Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 7 page  AMERICAN MICROSYSTEMS, INC. April 2000 2 4.24.00 FS6128-04 / FS6128-05 / FS6128-06 FS6128-04 / FS6128-05 / FS6128-06 FS6128-04 / FS6128-05 / FS6128-06 FS6128-04 / FS6128-05 / FS6128-06 PLL Clock Generator IC with VCXO PLL Clock Generator IC with VCXO PLL Clock Generator IC with VCXO PLL Clock Generator IC with VCXO ISO9001 ISO9001 ISO9001 ISO9001 Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI U = Input with Internal Pull-Up; DI D = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME DESCRIPTION 1 AI XIN VCXO Feedback 2 P VDD Power Supply (+3.3V) 3 AI XTUNE VCXO Tune 4 P VSS Ground 5 DO CLK Clock Output 6 - n/c No Connection 7 DO VSS Ground 8 AO XOUT VCXO Drive 3.0 Functional Block Description 3.1 Voltage-Controlled Crystal Oscillator (VCXO) The VCXO provides a tunable, low-jitter frequency refer- ence for the rest of the FS6128 system components. Loading capacitance for the crystal is internal to the FS6128. No external components (other than the reso- nator itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accom- plished by varying the voltage on the XTUNE pin. The value of this voltage controls the effective capacitance presented to the crystal. The actual amount that this load capacitance change will alter the oscillator frequency de- pends on the characteristics of the crystal as well as the oscillator circuit itself. It is important that the crystal load capacitance is speci- fied correctly to “center” the tuning range. See Table 5. A simple formula to obtain the “pulling” capability of a crystal oscillator is: () () ( ) C C C C C C C ppm f L L L L 1 0 2 0 6 1 2 1 2 10 ) ( + × + × × − × = ∆ where: C0 = the shunt (or holder) capacitance of the crystal C1 = the motional capacitance of the crystal CL1 and CL2 = the two extremes (minimum and maximum) of the applied load capacitance presented by the FS6128. EXAMPLE: A crystal with the following parameters is used: C1 = 0.025pF and C0 = 6pF. Using the minimum and maximum CL1 = 10pF, and CL2 = 20pF, the tuning range (peak-to-peak) is: () () ( ) ppm . f 300 10 6 20 6 2 106 10 20 025 0 = + × + × × − × = ∆ . 3.2 Phase-Locked Loop (PLL) The on-chip PLL is a standard frequency- and phase- locked loop architecture. The PLL multiplies the reference oscillator frequency to the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise specified). |
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