PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 3 of 12
Cost
The cost of both the component and manufacturing overhead
of battery-backed SRAM is high. In addition, there is a built-in
rework step required for battery attachment in case of surface
mount assembly. This can be eliminated with MRAM. In the
case of DIP battery-backed modules, the assembly
techniques are constrained to through-hole assembly and
board wash using no water.
System Reliability
Battery-backed SRAM is inherently vulnerable to shock and
vibration. In addition, a negative voltage on any pin of a
battery-backed SRAM, even a momentary undershoot, can
cause data loss. The negative voltage causes current to be
drawn directly from the battery, weakens the battery, and
reduces its capacity over time. In general, there is no way to
monitor the lost battery capacity. MRAM guarantees reliable
operation across the voltage range with inherent nonvolatility.
Space
Battery-backed SRAM in DIP modules takes up board space
height and dictates through-hole assembly. MRAM is offered
in surface mount as well as DIP packages.
Field Maintenance
Batteries must eventually be replaced, which creates an
inherent maintenance problem. Despite projections of long
life, it is difficult to know how long a battery will last, considering
all the factors that degrade them.
Environmental
Lithium batteries are a potential disposal burden and are
considered a fire hazard. MRAM eliminates all such issues
through a truly monolithic nonvolatile solution.
Users replacing battery-backed SRAMs with an integrated
Real-time Clock (RTC) in the same package may need to
move the RTC function to a different location within the
system.
EEPROM Replacement
CY9C6264 can also replace EEPROM in current applications.
CY9C6264 is pinout- and functionally-compatible to byte-wide
EEPROM, but it does not need data-bar polling, page Write,
and hardware Write protect due to its fast Write and
inadvertent Write-protect features.
Users replacing EEPROMs with MRAM can eliminate the
page mode operation and simplify to standard asynchronous
write. Additionally, data-bar polling can be eliminated, since
every byte Write is completed within same cycle. All Writes are
completed within 70 ns.
FeRAM Replacement
FeRAM requires addresses to be latched on falling edge of
CE, which adds to system overhead in managing the CE and
latching function. MRAM eliminates this overhead by offering
a simple asynchronous SRAM interface.
Users replacing FeRAM can simplify their address decoding
since you do not need to drive CE active and then inactive for
each address. This overhead is eliminated when using MRAM.
Secondly, MRAM Read is nondestructive and no precharge
cycle is required like the one used with FeRAM. This has no
apparent impact to the design, but the Read cycle time can
now see immediate improvement equal to the precharge time.
Boot Up PROM (EPROM, PROM) Function Replacement
The CY9C6264 can be accessed like an EPROM or PROM.
When CE1 and OE are LOW and CE2 and WE are HIGH, the
data stored at the memory location determined by the address
pins is asserted on the outputs. MRAM may be used to accom-
plish system boot up function using this condition.
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