Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial

Interface

4

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL TIMING (Figure 4, Note 8)

SCL Clock Frequency

400

kHz

Setup Time for START Condition

0.6

µs

Hold Time for START Condition

0.6

µs

SCL High Time

0.6

µs

SCL Low Time

1.3

µs

Data Setup Time

100

ns

Data Hold Time

0

0.9

µs

SDA, SCL Rise Time

300

ns

SDA, SCL Fall Time

300

ns

Setup Time for STOP Condition

0.6

µs

Bus Free Time Between a STOP

and START Condition

1.3

µs

Pulse Width of Spike Suppressed

50

ns

Maximum Capacitive Load for

Each Bus Line

(Note 9)

400

pF

Write NV Register Busy Time

(Note 10)

15

ms

NONVOLATILE MEMORY RELIABILITY

Data Retention

50

Years

200,000

Endurance

50,000

Stores

Note 2: Guaranteed monotonic.

Note 3: Gain error is defined as:

0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.

Note 5: Output settling time is measured from the 50% point of the rising edge of the last SCL of the data byte to 0.5 LSB of OUT_’s

final value for a code transition from 10 hex to F0 hex.

Note 6: Crosstalk is defined as the coupling from a DAC switching from code 00 hex to code FF hex to any other DAC that is in a

steady state at code 00 hex.

Note 7: Reference feedthrough is defined as the coupling from one driven reference with input code = FF hex to any other DAC

output with the reference of the DAC at a constant value and input code = 00 hex.

Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to

this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.

Note 10: The busy time begins from the initiation of the stop pulse.

256

00

×−

−

()

,,

_

V

ZCE

V

V

F Meas

F Ideal

REFH