Electronic Components Datasheet Search |
|
DM9095 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
|
DM9095 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 21 page DM9095 Twisted-Pair Medium Attachment Unit Final 10 Version: DM9095-DS-F02 August 21, 2000 Link Integrity Functions In the absence of receive traffic, the twisted-pair receiver on the chip can detect periodic link-integrity pulse is a 100ns high signal with pre-distortion followed by a return to idle. The chip provides a link-integrity reception window, during which a link pulse is expected in the absence of receive traffic. The link-integrity window nominally opens 6.5ms after the receipt of a link-integrity pulse or the end of a data frame. The window closes nominally 104ms after the receipt of a link-integrity pulse or the end of a data frame. If a link pulse is received before the link-integrity reception window opens, it is ignored. If no link-integrity pulse is received while the link-integrity reception window is open, there is a link failure. The RLED indicator is turned off, and the chip’s transmit, loopback, and receive functions are disabled. If a link-integrity pulse or receive traffic is received while the link-integrity reception window is open, the timers involved are reset. Once the DM9095 has detected a link failure, one of two events must occur before the DM9095 re-enables transmission and reception of data. The first possible event is the reception of two consecutive link-integrity pulses that both fall within the link-integrity reception window and are separated by at least a nominal 6.5ms. The second possible event is the reception of a data packet from the twisted pair. With either of these events, the TPMAU enters a wait state and continues to disable loopback, transmit, and receive functions. This continues until the DM9095 determines that there is no traffic going in either the transmit or receive direction and then enters the idle state. When the link integrity function is enabled, the DM9095 also transmits link-integrity pulses onto the transmit twisted-pair link. In the absence of transmit traffic, a link-integrity pulse is transmitted at a nominal rate of once per 16ms. Link-integrity pulses continue to be transmitted when the part is jabbed by the watchdog timer or there is link-integrity failure. Auto-Polarity Detection and Correction Functions The DM9095 can determine if the receive twisted pair has been wired with a polarity reversal. If so, the DM9095 automatically corrects for this error condition, when the correction function is enabled. Also, the AP pin itself can be connected to an LED to display the status of the polarity of the receive twisted pair. When enabled, the DM9095 powers up the function in the normal state and determines if the receive wires are reversed. The DM9095 examines either the IDL pulse at the end of each receive packet or the link pulse when the link integrity function is enabled and uses this information to sense the polarity. If the DM9095 determines that the incoming IDL pulse is of the proper polarity, it remains in normal state. If the DM9095 detects two consecutive reverse IDL pulses or two reverse link pulses, it enters reverse state. If the DM9095 determines that the polarity of the link is reversed, it internally corrects for the polarity, ensuring that all follow-on packets are sent up the AUI with the correct polarity. Automatic AUI and RJ45 Connector Selection Functions The chip provides the designer of a 10BASE-T Ethernet interface card with the ability to design a card without having to provide a switch or jumper array to change between AUI and twisted-pair connections. The DM9095 provides automatic changeover whenever the external cable connection is changed. When the link integrity function is enabled and twisted-pair cable is disconnected, all incoming receive signals disappear and the device places the CI + / CI – and DI + / DI – outputs in their high-impedance state. In addition, DO + / DO – inputs are high-impedance inputs. Power-Down Mode Function The power-down function is ideal for embedded, laptop computer applications. In power-down mode, the chip pulls within 10uA. When the device is reactivated from power-down mode, normal transceiver operation will resume after the 3.2ms calibration sequence is completed. Power-On Reset Function The DM9095 uses a power-on reset sequence to place itself into a known digital state, to allow the analog sections to stabilize, and to calibrate the internal delay line. Depending on the power-down condition, initialization requires the following lengths of time: z Power-on reset: 3.2 ms z Power-down mode: 3.2 ms |
Similar Part No. - DM9095 |
|
Similar Description - DM9095 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |