Electronic Components Datasheet Search |
|
CH7005C-T Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
|
CH7005C-T Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 49 page CHRONTEL CH7005C 4 201-0000-025 Rev 2.1, 8/2/99 Table 1. Pin Descriptions 44-Pin PLCC 44-Pin TQFP Type Symbol Description 21-15 13-12, 10-4 15,14, 13,12, 11,10, 9,7,6, 4,3, 2,1, 44,43, 42 In D15-D0 Digital Pixel Inputs These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or 16-bit non-multiplexed formats, determined by the input mode setting (see Registers and Programming section). Inputs D0 - D7 are used when operating in 8-bit multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs D0 - D15 are used when operating in 16-bit mode. The data structure and timing sequence for each mode is described in the section on Digital Input Port. 43 37 Out P-OUT Pixel Clock Output The CH7005, operating in master mode, provides a pixel data clocking signal to the VGA controller. This clock will only be provided in master clock modes and will be tri-stated otherwise. This pin provides the pixel clock output signal (adjustable as 1X,2X or 3x) to the VGA controller (see the section on Digital Video Interface, Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. 1 39 In XCLK Pixel Clock Input To operate in a pure master mode, the P-OUT signal should be connected to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7005 accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum. 3 41 In/Out V Vertical Sync Input/Output This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical sync to the VGA controller. The capacitive loading on this pin should kept to a minimum. 2 40 In/Out H Horizontal Sync Input/Output This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal sync to the VGA controller. The capacitive loading on this pin should be kept to a minimum. 41 35 In/Out DS/BCO Data/Start (input) / Buffered Clock (output) When configured as an input, the rising edge of this signal identifies the first active pixel of data for each active line. When configured as an output this pin provides a buffered clock output. The output clock can be selected using the BCO register (17h) (see Registers and Programming). 38 32 In XI Crystal Input A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. 39 33 In XO/FIN Crystal Output or External Fref A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. |
Similar Part No. - CH7005C-T |
|
Similar Description - CH7005C-T |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |