 |
 |
|
| LAN9115 |
|
|||||||||||||||
 SMSC
|
| |||||||||||||||
|
1 page 
SMSC LAN9115 PRODUCT PREVIEW Revision 0.1 (12-20-04) Data Brief PRODUCT FEATURES LAN9115 Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Highlights ■ Member of LAN9118 Family; optimized for medium- performance applications ■ Easily interfaces to most 16-bit embedded CPU’s ■ Efficient architecture with low CPU overhead ■ Integrated PHY; supports external PHY via MII interface ■ Supports audio & video streaming over Ethernet: multiple standard-definition (SD) MPEG2 streams ■ Medium-speed member of LAN9118 Family (all members are pin-compatible) Target Applications ■ Printers, kiosks, security systems ■ General embedded applications ■ Audio distribution systems ■ Basic Cable, satellite, and IP set-top boxes ■ Video-over IP Solutions, IP PBX & Video Phones ■ Wireless routers & access points ■ Digital video recorders Key Benefits ■ Non-PCI Ethernet controller for medium-performance applications — 16-bit interface — Burst-mode read support ■ Eliminates dropped packets — Internal SRAM can store over 200 packets — Supports automatic or host-triggered PAUSE and back- pressure flow control ■ Minimizes CPU overhead — Supports Slave-DMA — Interrupt Pin with Programmable Hold-off timer ■ Reduces system cost and increases design flexibility — SRAM-like interface easily interfaces to most Embedded CPU’s or SoC’s — Low-cost, low-pin count non-PCI interface for embedded designs ■ Reduced-Power Modes — Numerous power management modes — Wake on LAN — Magic packet wakeup — Wakeup indicator event signal — Link Status Change ■ Single chip Ethernet controller — Fully compliant with IEEE 802.3/802.3u standards — Integrated Ethernet MAC and PHY — 10BASE-T and 100BASE-TX support — Full- and Half-duplex support — Full-duplex flow control — Backpressure for half-duplex flow control — Preamble generation and removal — Automatic 32-bit CRC generation and checking — Automatic payload padding and pad removal — Loop-back modes ■ Flexible address filtering modes — One 48-bit perfect address — 64 hash-filtered multicast addresses — Pass all multicast — Promiscuous mode — Inverse filtering — Pass all incoming with status report — Disable reception of broadcast packets ■ Integrated Ethernet PHY — Auto-negotiation — Automatic polarity detection and correction ■ Efficient host bus interface — Simple, SRAM-like interface — 16-bit data bus — Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions — One configurable Host interrupt ■ Miscellaneous features — Low profile 100-pin TQFP package; green, lead-free package also available — Integral 1.8V regulator — General Purpose Timer — Support for optional EEPROM — Support for 3 status LEDs multiplexed with Programmable GPIO signals ■ 3.3V Power Supply with 5V tolerant I/O ■ 0 to 70°C |
