Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

IDT72T36125L4BBI Datasheet(PDF) 8 Page - Integrated Device Technology

Part # IDT72T36125L4BBI
Description  2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
Download  57 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72T36125L4BBI Datasheet(HTML) 8 Page - Integrated Device Technology

Back Button IDT72T36125L4BBI Datasheet HTML 4Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 5Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 6Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 7Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 8Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 9Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 10Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 11Page - Integrated Device Technology IDT72T36125L4BBI Datasheet HTML 12Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 57 page
background image
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
PRS
PartialReset
HSTL-LVTTL
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q35 DataOutputs
HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not
OUTPUT
be connected. Outputs are not 5V tolerant regardless of the state of
OE and RCS.
RCLK/
Read Clock/
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by
REN,therisingedgeofRCLK
RD
Read Stobe
INPUT
reads data from the FIFO memory and offsets from the programmable registers. If
LD is LOW, the values
loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read
port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
REN
should be tied LOW.
RCS
Read Chip Select
HSTL-LVTTL
RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterResetorPartialResetthe
RCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance
regardless of
RCS.
REN
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected,
REN enablesRCLK for reading data from the
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the
REN
input should be tied LOW.
RHSTL
(1) Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select
INPUT
required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmit
HSTL-LVTTL
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EFflag to LOW (OR to
INPUT
HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode
or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump
to the ‘mark’ location.
SCLK
Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN is enabled.
SEN
Serial Enable
HSTL-LVTTL
SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL
System HSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
INPUT
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input
INPUT
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Output
OUTPUT
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
TMS(2)
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
Select
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2) JTAGReset
HSTL-LVTTL
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use
TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
WEN
WriteEnable
HSTL-LVTTL When Synchronous operation of the write port has been selected,
WEN enables WCLK for writing data into
INPUT
theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
WCS
WriteChipSelect
HSTL-LVTTL The
WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WCLK/
WriteClock/
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by
WEN,therisingedgeofWCLK
WR
WriteStrobe
INPUT
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (
WEN should be tied to its active state).


Similar Part No. - IDT72T36125L4BBI

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT72T36125 IDT-IDT72T36125 Datasheet
472Kb / 57P
   2.5 VOLT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS
IDT72T36125 IDT-IDT72T36125 Datasheet
359Kb / 56P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
logo
Renesas Technology Corp
IDT72T36125 RENESAS-IDT72T36125 Datasheet
564Kb / 58P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
FEBRUARY 2009
IDT72T36125 RENESAS-IDT72T36125 Datasheet
475Kb / 57P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
JUNE 2017
More results

Similar Description - IDT72T36125L4BBI

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT72T36105 IDT-IDT72T36105 Datasheet
359Kb / 56P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
logo
Renesas Technology Corp
IDT72T36105 RENESAS-IDT72T36105 Datasheet
475Kb / 57P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
JUNE 2017
IDT72T3645 RENESAS-IDT72T3645 Datasheet
564Kb / 58P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS
FEBRUARY 2009
logo
Integrated Device Techn...
72T72115L5BBGI IDT-72T72115L5BBGI Datasheet
471Kb / 53P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
IDT72T7285 IDT-IDT72T7285 Datasheet
542Kb / 53P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
72T7285 IDT-72T7285 Datasheet
358Kb / 54P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
logo
Renesas Technology Corp
IDT72T7285 RENESAS-IDT72T7285 Datasheet
560Kb / 55P
   2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
JUNE 2017
logo
Integrated Device Techn...
IDT72T3645 IDT-IDT72T3645_09 Datasheet
472Kb / 57P
   2.5 VOLT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS
IDT72T7285 IDT-IDT72T7285_09 Datasheet
465Kb / 53P
   2.5 VOLT HIGH-SPEED TeraSync FIFO 72-BIT CONFIGURATIONS
IDT72T1845 IDT-IDT72T1845_09 Datasheet
510Kb / 55P
   2.5 VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com