9

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

IDT72255LA/72265LA SUPERSYNC FIFO™

8,192 x 18, 16,384 x 18

Figure 4. Programmable Flag Offset Programming Sequence

Figure 3. Offset Register Location and Default Values

Selection

Parallel write to registers:

Empty Offset

Full Offset

Parallel read from registers:

Empty Offset

Full Offset

No Operation

Write Memory

Read Memory

No Operation

4670 drw 07

0

0

X

1

1

1

0

0

1

1

0

X

1

1

1

0

1

X

0

1

1

Serial shift into registers:

26 bits for the 72255LA

28 bits for the 72265LA

1

1

1

X

X

X

0

WCLK

X

X

X

X

RCLK

X

X

X

X

X

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

EMPTY OFFSET REGISTER

17

0

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

FULL OFFSET REGISTER

17

0

DEFAULT VALUE

DEFAULT VALUE

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

12

12

72255LA – 8,192 x 18–BIT

4670 drw 06

EMPTY OFFSET REGISTER

17

0

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

FULL OFFSET REGISTER

17

0

DEFAULT VALUE

DEFAULT VALUE

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

13

13

72265LA – 16,384 x 18–BIT

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.