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IDT70V7339S133BC Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT70V7339S133BC Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 22 page 6.42 IDT70V7339S High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges 5 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/ WL R/ WR Read/Write Enable OEL OER Output Enable BA0L - BA5L BA0R - BA5R Bank Address(4) A0L - A12L A0R - A12R Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock PL/ FTL PL/ FTR Pipeline/Flow-Through ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable REPEATL REPEATR Counter Repeat(3) LBL, UBL LBR, UBR Byte Enables (9-bit bytes) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) OPTL OPTR Option for selecting VDDQX(1,2) VDD Power (3.3V)(1) VSS Ground (0V) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) TMS Test Mode Select TRST Reset (Initialize TAP Controller) 5628 tbl 01 NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4. Accesses by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory with the shared array that is not currently being accessed by the opposite port (i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the ports within that bank may be corrupted (in the case that either or both ports are writing) or may result in invalid output (in the case that both ports are trying to read). |
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