6.42

IDT70V7339S

High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

5

Pin Names

Left Port

Right Port

Names

Chip Enables

R/

R/

Read/Write Enable

Output Enable

Address

Data Input/Output

Clock

PL/

PL/

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Byte Enables (9-bit bytes)

Ground (0V)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz)

TMS

Test Mode Select

TRST

Reset (Initialize TAP Controller)

5628 tbl 01

NOTES:

applying inputs on the I/Os and controls for that port.

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When

via

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).