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IDT70V7339S133BF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70V7339S133BF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 22 page ©2002 Integrated Device Technology, Inc. DECEMBER 2002 DSC 5628/6 1 Functional Block Diagram Features: x 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 8K x 18 banks – 9 megabits of memory on chip x Bank access controlled via bank address pins x High-speed data access – Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz) (max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) x Selectable Pipelined or Flow-Through output mode x Counter enable and repeat features x Dual chip enables allow for depth expansion without additional logic x Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time x Separate byte controls for multiplexed bus and bus matching compatibility x LVTTL- compatible, 3.3V (±150mV) power supply for core x LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port x Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz x Available in a 144-pin Thin Quad Flatpack (TQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) x Supports JTAG features compliant with IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 144-pin TQFP package. HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V7339S 8Kx18 MEMORY ARRAY (BANK 63) MUX MUX PL/ FTL OPTL CLKL ADSL CNTENL REPEATL R/ WL CE0L CE1L UBL LBL OEL I/O0L-17L A12L A0L JTAG 8Kx18 MEMORY ARRAY (BANK 1) MUX MUX 8Kx18 MEMORY ARRAY (BANK 0) MUX MUX CONTROL LOGIC I/O CONTROL BANK DECODE ADDRESS DECODE I/O0R-17R A12R A0R CONTROL LOGIC I/O CONTROL BANK DECODE ADDRESS DECODE 5628 drw 01 BA5R BA4R BA3R BA2R BA1R BA0R BA5L BA4L BA3L BA2L BA1L BA0L , PL/ FTR OPTR CLKR ADSR CNTENR REPEATR R/ WR CE0R CE1R UBR LBR OER TMS TCK TRST TDI TDO NOTE: 1. The Bank-Switchable dual-port uses a true SRAM core instead of the traditional dual-port SRAM core. As a result, it has unique operating characteristics. Please refer to the functional description on page 19 for details. |
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