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IDT5V9352PRI Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT5V9352PRI Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 10 page 5 INDUSTRIALTEMPERATURERANGE IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER Symbol Characteristic Test Conditions Min. Typ. Max. Unit tR,tF OutputRise/FallTime 0.55V to 2.4V 0.1 1 ns All Outputs, any frequency 200 tSK(O) OutputtoOutputSkew withinQAoutputbank 200 ps withinQBoutputbank 100 within QCoutputbank 100 fVCO PLL VCO Lock Range(2) 200 400 MHz ÷2output 100 200 ÷4output 50 100 fMAX MaximumOutputFrequency ÷6output 33.3 66.6 MHz ÷8output 25 50 ÷12output 16.67 33.3 tPW Output Duty Cycle 47 50 53 % tPD REFCLK to FBIN Delay fREF < 40MHz -200 +150 ps PLLLocked fREF > 40MHz, PLL locked -50 +150 tPLZ OutputDisableTime 8ns tPHZ MR/OE (LOW-HIGH) to any Q tPZL OutputEnableTime 10 ns tPZH MR/OE (HIGH-LOW) to any Q Outputfrequenciesmixed 400 tJ Cycle-to-Cycle Jitter Outputs in any ÷4 and ÷6 combination 250 ps Alloutputssamefrequency 100 Outputfrequenciesmixed 200 tJ(PER) PeriodJitter Outputs in any ÷4 and ÷6 combination 150 ps Alloutputssamefrequency 75 ÷4 feedback divider RMS (1σ)15 tJ( φ) I/O Phase Jitter ÷6 feedback divider RMS (1σ)20 ps ÷8 feedback divider RMS (1σ) 18-20 ÷12 feedback divider RMS (1σ)25 ÷4feedback 3 - 10 BW PLLClosedLoopBandwidth ÷6feedback 1.5 - 6 MHz ÷8feedback 1 - 3.5 ÷12feedback 0.5 - 2 tLOCK Maximum PLL Lock Time 10 ms AC ELECTRICAL CHARACTERISTICS(1) TA = –40°C to +85°C, VCC = 3.3V ± 5% NOTES: 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The input frequency on CCLK must match the VCO frequency range divided by the feedback divide ratio FB: freq. = fvco ÷÷÷÷÷ FB. |
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