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HT48RA0-2 Datasheet(PDF) 5 Page - Holtek Semiconductor Inc |
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HT48RA0-2 Datasheet(HTML) 5 Page - Holtek Semiconductor Inc |
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5 / 32 page  HT48RA0-2/HT48CA0-2 Rev. 1.50 5 July 23, 2004 higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remaining 2 bits are read as ²0². The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), where P indicates the table location. Before ac- cessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory used to save the contents of the program counter (PC) only. The stack is organized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call the contents of the program counter are pushed onto the stack. At the end of a subroutine sig- naled by a return instruction (RET), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a ²CALL² is subsequently exe- cuted, stack overflow occurs and the first entry will be lost (only the most recent return address is stored). Data Memory - RAM The data memory is designed with 42 ´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (32 ´8). Most of them are read/write, but some are read only. The special function registers include the indirect ad- dressing register (00H), the memory pointer register (MP;01H), the accumulator (ACC;05H) the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the status register (STATUS;0AH) and the I/O registers (PA;12H, PB;14H, PC;16H). The remaining space before the 20H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 20H to 3FH, is used for data and control informa- tion under instruction command. All data memory areas can handle arithmetic, logic, in- crement, decrement and rotate operations directly. Ex- cept for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through memory pointer register (MP;01H). Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the re- sult 00H. Writing indirectly results in no operation. The memory pointer register MP (01H) is a 6-bit register. The bit 7~6 of MP is undefined and reading will return the result ²1². Any writing operation to MP will only trans- fer the lower 6-bit data to MP. Accumulator The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. Data movement between two data memory locations has to pass through the accumulator. G e n e r a l P u r p o s e D A T A M E M O R Y ( 3 2 B y t e s ) S p e c i a l P u r p o s e D A T A M E M O R Y 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 3 F H I n d i r e c t A d d r e s s i n g R e g i s t e r M P A C C P C L T B L P T B L H S T A T U S P A P B P C : U n u s e d R e a d a s " 0 0 " 2 0 H RAM Mapping |
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