CY23FP12
Document #: 38-07246 Rev. *E
Page 6 of 10
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Supply Voltage
Non-functional
–0.5
7
VDC
VIN
Input Voltage REF
Relative to VCC
–0.5
7
VDC
VIN
Input Voltage Except REF
Relative to VCC
–0.5
VDD + 0.5
VDC
LUI
Latch-up Immunity
Functional
300
mA
TS
Temperature, Storage
Non-functional
–65
+125
°C
TA
Temperature, Operating Ambient
Commercial Temperature
0
+70
°C
TA
Temperature, Operating Ambient
Industrial Temperature
–40
+85
°C
TJ
Junction Temperature
Industrial Temperature
125
°C
ØJc
Dissipation, Junction to Case
Functional
34
°C/W
ØJa
Dissipation, Junction to Ambient
Functional
86
°C/W
ESDh
ESD Protection (Human Body Model)
2000
V
MSL
Moisture Sensitivity Level
MSL – 1
class
GATES
Total Functional Gate Count
Assembled Die
21375
each
UL–94
Flammability Rating
@ 1/8 in.
V–0
class
FIT
Failure in Time
Manufacturing test
10
ppm
TPU
Power-up time for all VDDs to reach
minimum specified voltage (power
ramps must be monotonic)
0.05
500
ms
DC Electrical Specifications for CY23FP12SC/I Commercial/Industrial Temperature Devices
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VDDC
Core Supply Voltage
3.135
3.465
V
VDDA, VDDB
Bank A, Bank B
Supply Voltage
3.135
3.465
V
2.375
2.625
V
VIL
Input LOW Voltage[3]
0.3 × VDD
V
VIH
Input HIGH Voltage[3]
0.7 × VDD
V
IIL
Input LOW Current[3] VIN = 0V
50.0
µA
IIH
Input HIGH Current[3] VIN = VDD
50.0
µA
VOL
Output LOW Voltage[4] VDDA/VDDB = 3.3V, IOL = 16 mA (standard drive)
VDDA/VDDB = 3.3V, IOL = 20 mA (high drive)
VDDA/VDDB = 2.5V, IOL = 16 mA (high drive)
0.5
V
VOH
Output HIGH
Voltage[4]
VDDA/VDDB = 3.3V, IOH = –16 mA (standard drive)
VDDA/VDDB = 3.3V, IOH = –20 mA (high drive)
VDDA/VDDB = 2.5V, IOH = –16 mA (high drive)
VDD – 0.5
V
IDDS
Power-down Supply
Current
REF = 0 MHz
12
50
µA
IDD
Supply Current
VDDA = VDDB = 2.5V, Unloaded outputs @ 166 MHz
40
65.0
mA
VDDA = VDDB = 2.5V, Loaded outputs @ 166 MHz,
CL = 15 pF
65
100
VDDA = VDDB = 3.3V, Unloaded outputs @ 166 MHz
50
80
VDDA = VDDB = 3.3V, Loaded outputs @ 166 MHz,
CL = 15 pF
100
120
Notes:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
