CY23FP12
Document #: 38-07246 Rev. *E
Page 5 of 10
Table 3 is a list of output dividers that are independently
selected to connect to each output pair.
In the default (non-programmable) state of the device, S1 and
S2 pins will function, as indicated in Table 4.
Field Programming the CY23FP12
The CY23FP12 is programmed at the package level, i.e. in a
programmer socket. The CY23FP12 is flash-technology
based, so the parts can be reprogrammed up to 100 times.
This allows for fast and easy design changes and product
updates, and eliminates any issues with old and out-of-date
inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large production quantities.
CyberClocks
Software
CyberClocks is an easy-to-use software application that
allows the user to custom-configure the CY23FP12. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyberClocks
outputs an industry standard JEDEC file used for
programming the CY23FP12.
CyberClocks can be downloaded free of charge from the
Cypress website at www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY23FP12 and
program samples and small prototype quantities. The kit
comes with the latest version of CyberClocks and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyberClocks can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
CY23FP12 Frequency Calculation
The CY23FP12 is an extremely flexible clock buffer with up to
twelve individual outputs, generated from an integrated PLL.
There are four variables used to determine the final output
frequency. These are the input Reference Frequency M, the N
dividers, and the post divider X.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs pair has many output options available to it.
There are six post divider options: /1, /2, /3, /4, /X, and /2X.
The post divider options can be applied to the calculated PLL
frequency or to the REF directly. The feedback either is
connected to CLKA0 internally or connected to any output
externally.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
So the output can be calculated as following:
FREF / M = FFBK / N.
FPLL = (FREF * N * post divider)/M.
FOUT = FPLL / post divider.
In addition to above divider options, the another option
bypasses the PLL and passes the REF directly to the output.
FOUT = FREF.
Note:
1. Outputs will be rising edge aligned only to those outputs using this same device setting.
2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is
set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If
CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
Table 3.
CLKA/B Source
Output Connects To
0 [000]
REF
1 [001]
Divide by 1
2 [010]
Divide by 2
3 [011]
Divide by 3
4 [100]
Divide by 4
5 [101]
Divide by X
6 [110]
Divide by 2X[1]
7 [111]
TEST mode [LOCK signal][2]
Table 4.
S2
S1
CLKA[5:0]
CLKB[5:0]
Output
Source
0
0
Three-state
Three-state
PLL
0
1
Driven
Three-state
PLL
1
0
Driven
Driven
Reference
1
1
Driven
Driven
PLL
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