CY7C1031-12JC datasheet(3/13 Pages) CYPRESS

Part #	CY7C1031-12JC

Description	64K x 18 Synchronous Cache RAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1031

CY7C1032

Document #: 38-05278 Rev. *A

Page 3 of 13

Application Example

Figure 1 shows a 512-Kbyte secondary cache for the Pentium

microprocessor using four CY7C1031 cache RAMs.

PENTIUM

CLK

DATA

ADR

66-MHz OSC

CACHE

CLK

DATA

ADR

CLK

DATA

ADR

MATCH

DIRTY

VALID

MATCH

DIRTY

VALID

CD

ADSP

ADSC ADV OE WH0,

WL0

CACHE

CONTROLLER

CLK

DATA

ADR

ADSP

ADSC

ADV

OE

WH, WL

512 KB

7C1031

INTERFACE TO

MAIN MEMORY

WH,WL

WH1,

WL1

WH2,

WL2

WH3,

WL3

2

22

ADS

PROCESSOR

TAG

Figure 1. Cache Using Four CY7C1031s

Pin Definitions

Signal Name

Type

# of Pins

Description

VCC

Input

1

+5V Power

VCCQ

Input

4

+5V or 3.3V (Outputs)

GND

Input

1

Ground

VSSQ

Input

4

Ground (Outputs)

CLK

Input

1

Clock

A15 – A0

Input

16

Address

ADSP

Input

1

Address Strobe from Processor

ADSC

Input

1

Address Strobe from Cache Controller

WH

Input

1

Write Enable – High Byte

WL

Input

1

Write Enable – Low Byte

ADV

Input

1

Advance

OE

Input

1

Output Enable

CS

Input

1

Chip Select

DQ15–DQ0

Input/Output

16

Regular Data

DP1–DP0

Input/Output

2

Parity Data

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