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AT89LP2052 Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT89LP2052 Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 89 page  11 3547A–MICRO–3/05 AT89LP2052/LP4052 [Preliminary] 11. Reset During reset, all I/O Registers are set to their initial values, the port pins are tri-stated, and the program starts execution from the Reset Vector, 0000H. The AT89LP2052/LP4052 has four sources of reset: power-on reset, brown-out reset, external reset, and watchdog reset. 11.1 Power-on Reset A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The POR is activated whenever V CC is below the detection level. The POR cir- cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices without a brown-out detector. The POR circuit ensures that the device is reset from power-on. When V CC reaches the Power-on Reset threshold voltage, the POR delay counter determines how long the device is kept in POR after V CC rise. The POR signal is activated again, without any delay, when V CC falls below the POR threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. 11.2 Brown-out Reset The AT89LP2052/LP4052 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V CC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is nominally 2.2V. The purpose of the BOD is to ensure that if V CC fails or dips while executing at speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution. When V CC decreases to a value below the trigger level, the Brown-out Reset is imme- diately activated. When V CC increases above the trigger level, the BOD delay counter starts the MCU after the time-out period has expired. 11.3 External Reset The RST pin functions as an active-high reset input. The pin must be held high for at least two clock cycles to trigger the internal reset. RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external reset pin is held high and the ISP Enable fuse is enabled. 11.4 Watchdog Reset When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles. Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times out. A Watchdog reset will occur only if the Watchdog has been enabled. The Watchdog is dis- abled by default after any reset and must always be re-enabled if needed. 12. Power Saving Modes The AT89LP2052/LP4052 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. |
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