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ATC18RHA Datasheet(PDF) 2 Page - ATMEL Corporation |
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ATC18RHA Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 20 page 2 4261B–AERO–06/05 ATC18RHA • MAX conditions: –– TJ = +125°C –– VDD (cell) = 1.65V – – Process = slow (1.1) Overview Introduction The ASIC ATC18RHA Design Manual presents all the required information and flows for 0.18µm designs for aerospace applications, allowing users to view Atmel specific or standard commer- cial tool kits and methodological details for actual implementations. This offering is a 0.18µm CMOS technology based, using 5 Metal layers, and specified with the 1.8V or 3.3V ranges for the periphery, and with the 1.8V range for the core. The technology parameters and some extra features are described here after. Periphery Buffers Description The peripheral buffer (also called pad) is the electrical interface between the external signals (voltage range from 0 to 3.3V) and the internal core signals (from 0 to 1.8V). Several Power Supply rails are used inside the chip. The ATC18RHA buffer family is split into: • IO18 family: VCCB = 1.8V (1.65V to 1.95V) • IO33 family: VCCB = 3.3V (3V to 3.6V) Both IO18 and IO33 families contain: • Bidirectional pads • Tristate Output pads • Output Only pads • Input Only pads (Inverting,Non-Inverting,Schmitt Trigger) Furthermore the Bidirectional, Tristate Ouputs and Input Only pads are available with or without Pull-Up or Pull-Down structures. The IO33 family also contains specific pads: • 3.3V PCI Bidirectional, Tristate Output and Output Only pads • LVDS transmitter and Receiver differential pads • LVPECL Receiver differential pads Standard pads Input level compatibility • IO18: CMOS • IO33: CMOS,LVTTL compatible |
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