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ATWINC15X0 Datasheet(PDF) 24 Page - Microchip Technology |
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ATWINC15X0 Datasheet(HTML) 24 Page - Microchip Technology |
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24 / 54 page  Parameter Min. Max. Units Description Notes together. VDDIO must not rise before VBATT. tB 0 ms VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. tC 5 ms CHIP_EN rise to RESETN rise This delay is needed because the XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating. tA’ 0 ms VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO. tB’ 0 ms CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously. tC’ 0 ms RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously. 8.5 Digital I/O Pin Behavior During Power-up Sequences The following table represents digital I/O Pin states corresponding to device power modes. Table 8-3. Digital I/O Pin Behavior in Different Device States Device state VDDIO CHIP_EN RESETN Output driver Input driver Pull up/down resistor (96kΩ) Power-Down: core supply off High Low Low Disabled (Hi-Z) Disabled Disabled Power-on Reset: core supply on, hard reset on High High Low Disabled (Hi-Z) Disabled Enabled Power-On Default: core supply on, the device is out of reset but not programmed yet High High High Disabled (Hi-Z) Enabled Enabled On Sleep/ On Transmit/ On Receive: core supply on, device programmed by firmware High High High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled ATWINC15x0 Power Consumption © 2017 Microchip Technology Inc. Datasheet DS70005304B-page 24 |
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