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MRF24XA Datasheet(PDF) 82 Page - Microchip Technology |
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MRF24XA Datasheet(HTML) 82 Page - Microchip Technology |
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82 / 258 page  MRF24XA DS70005023C-page 82 Preliminary 2015 Microchip Technology Inc. REGISTER 3-12: PIR4 (PERIPHERAL INTERRUPT REGISTER 4) ADDRESS: 0x07 REGISTER 3-13: PIE4 (PERIPHERAL INTERRUPT ENABLE 4) ADDRESS: 0x0B R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 R/W/HS/HC-0 TXSFDIF RXSFDIF ERRORIF WARNIF EDCCAIF GPIO2IF GPIO1IF GPIO0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown r = Reserved bit 7-3 Out of scope bit 2 GPIO2IF: GPIO2 Interrupt Flag bit Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and configured to input and the level matches with the polarity. bit 1 GPIO1IF: GPIO1 Interrupt Flag bit Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and configured to input and the level matches with the polarity. bit 0 GPIO0IF: GPIO0 Interrupt Flag bit Set by the device if the GPIOMODE register is set to normal operation, the GPIO is enabled and configured to input and the level matches with the polarity. R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 TXSFDIE RXSFDIE ERRORIE WARNIE EDCCAIE GPIO2IE GPIO1IE GPIO0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown r = Reserved bit 7-3 Out of scope bit 2 GPIO2IE: GPIO2 Interrupt Enable bit This bit masks the GPIO2IF interrupt register. bit 1 GPIO1IE: GPIO1 Interrupt Enable bit This bit masks the GPIO1IF interrupt register. bit 0 GPIO0IE: GPIO0 Interrupt Enable bit This bit masks the GPIO0IF interrupt register. |
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