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BQ25122YFPR Datasheet(PDF) 5 Page - Texas Instruments |
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BQ25122YFPR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 70 page  5 bq25122 www.ti.com SLUSD33 – NOVEMBER 2017 Product Folder Links: bq25122 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. IPRETERM D1 I Termination current programming input. Connect a 0- Ω to 10-kΩ resistor from IPRETERM to GND to program the termination current between 5% and 20% of the charge current. The pre-charge current is the same as the termination current setting. Connect IPRETERM to GND to set the termination current to the internal default threshold. IPRETERM can also be updated through I2C. INT D2 O Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during charging. INT is high impedance when charging is complete, disabled, or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT bit in the control register. Connect INT to a logic rail using an LED for visual indication of charge status or through a 100kΩ resistor to communicate with the host processor. PG D4 O Open-drain Power Good status indication output. PG pulls to GND when VIN is above V(BAT) + VSLP and less that VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic voltage rail using a 1k Ω to 100kΩ resistor, or use with an LED for visual indication. PG can also be configured as a push-button voltage shifted output (MRS) in the registers, where the output of the PG pin reflects the status of the MR input, but pulled up to the desired logic voltage rail using a 1k Ω to 100kΩ resistor. RESET D3 O Reset Output. RESET is an open drain active low output that goes low when MR is held low for longer than tRESET, which is configurable by the MRRESET registers. RESET is deasserted after the tRESET_D, typically 400ms. MR E1 I Manual Reset Input. MR is a push-button input that must be held low for greater than tRESET to assert the reset output. If MR is pressed for a shorter period, there are two programmable timer events, tWAKE1 and tWAKE2, that trigger an interrupt to the host. The MR input can also be used to bring the device out of Ship mode. SW A4 O Inductor Connection. Connect to the switched side of the external inductor. SYS B5 I System Voltage Sense Connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance. LS/LDO C5 O Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to assure stability. Be sure to account for capacitance bias voltage derating when selecting the capacitor. VINLS B4, C4 I Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from this pin to GND. BAT B1, B2 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at least 1 µF of ceramic capacitance. TS C3 I Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to GND. The NTC is connected from TS to GND. The TS function provides four thresholds for JEITA compatibility. TS faults are reported by the I2C interface during charge mode. |
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