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ATSAMB11XR Datasheet(PDF) 27 Page - Microchip Technology |
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ATSAMB11XR Datasheet(HTML) 27 Page - Microchip Technology |
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27 / 87 page  Table 7-1. NVIC Register Summary Name Description ISER Interrupt Set-Enable Register ICER Interrupt Clear-Enable Register ISPR Interrupt Set-Pending Register ICPR Interrupt Clear-Pending Register IPR0-IPR7 Interrupt Priority Registers Note: For a description of each register, see the Cortex-M0 documentation from ARM. The Cortex-M0 NVIC is connected to 32 IRQ sources. Some of the interrupt sources are marked reserved for internal operation of the BLE functionality and ROM code of the ATSAMB11. The following table lists the interrupts that are available in ATSAMB11. Also, some of the interrupts are marked as RESERVED as they are used by the BLE stack and are used for firmware in general. Applications must refrain from registering an ISR for those interrupts as it affects the chip functionality. Table 7-2. ATSAMB11 Interrupts ISR index Interrupt Source Availability 0 UART0 RX Available/Muxable 1 UART0 TX Available/Muxable 2 UART1 RX Available/Muxable 3 UART1 TX Available/Muxable 4 SPI0 RX Available/Muxable 5 SPI0 TX Available/Muxable 6 SPI1 RX Available/Muxable 7 SPI1 TX Available/Muxable 8 I2C0 RX Available/Muxable 9 I2C0 TX Available/Muxable 10 I2C1 RX Available/Muxable 11 I2C1 TX Available/Muxable 12 Watchdog 0 RESERVED 13 Watchdog 1 Available/Muxable 14 ARM ® Dual Timer Available/Muxable 15 BLE specific RESERVED 16 RESERVED Available/Muxable 17 BLE specific RESERVED 18 SPI Flash Available/Muxable ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 27 |
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