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AMIC120 Datasheet(PDF) 32 Page - Texas Instruments |
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AMIC120 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 239 page  Copyright © 2017, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AMIC120 32 AMIC120 SPRSP09 – DECEMBER 2017 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] AA2 ddr_dqsn3 ddr_dqsn3 0x0 IO PU Mode0 VDDS_DDR Yes 8 PU/PD LVCMOS/HST L/HSUL_12 M1 ddr_nck ddr_nck 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 U1 ddr_odt0 ddr_odt0 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 U2 ddr_odt1 ddr_odt1 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 N2 ddr_rasn ddr_rasn 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 T1 ddr_resetn ddr_resetn 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS T6 ddr_vref ddr_vref 0x0 AP (19) NA NA Mode0 VDDS_DDR NA NA NA Analog AC3 ddr_vtp ddr_vtp 0x0 I (20) NA NA Mode0 VDDS_DDR NA NA NA Analog N4 ddr_wen ddr_wen 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 A24 dss_ac_bias_en dss_ac_bias_en 0x0 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS gpmc_a11 0x1 O gpmc_a4 0x2 O pr1_edio_data_in5 0x3 I pr1_edio_data_out5 0x4 O pr0_pru1_gpo9 0x5 O pr0_pru1_gpi9 0x6 I gpio2_25 0x7 IO B22 dss_data0 (4) dss_data0 0x0 IO OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS gpmc_a0 0x1 O pr1_mii_mt0_clk 0x2 I ehrpwm2A 0x3 O pr1_pru0_gpo0 0x5 O pr1_pru0_gpi0 0x6 I gpio2_6 0x7 IO A21 dss_data1 (4) dss_data1 0x0 IO OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS gpmc_a1 0x1 O pr1_mii0_txen 0x2 O ehrpwm2B 0x3 O pr1_pru0_gpo1 0x5 O pr1_pru0_gpi1 0x6 I gpio2_7 0x7 IO |
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