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ADS7142 Datasheet(PDF) 23 Page - Texas Instruments |
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ADS7142 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 74 page  Copyright © 2017, Texas Instruments Incorporated R1 R2 AVDD ADDR 23 ADS7142 www.ti.com SBAS773A – SEPTEMBER 2017 – REVISED DECEMBER 2017 Product Folder Links: ADS7142 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Tolerance for R1,R2 < ±5% (2) DNP = Do not populate Figure 45. External Resistor Connection Diagram for ADDR Pin Table 2. I2C Address Selection Resistors Address R1 (1) R2(1) 0 Ω DNP(2) 0011111b (1Fh) 11 kΩ DNP(2) 0011110b (1Eh) 33 kΩ DNP(2) 0011101b (1Dh) 100 kΩ DNP(2) 0011100b (1Ch) DNP(2) 0Ω or DNP(2) 0011000b (18h) DNP(2) 11 kΩ 0011001b (19h) DNP(2) 33 kΩ 0011010b (1Ah) DNP(2) 100 kΩ 0011011b (1Bh) 7.3.7 Data Buffer When operating in Autonomous Monitoring Mode, the device can use the internal data buffer for data storage. The internal data buffer is 16-bit wide and 16-word deep and follows the FIFO (first-in, first-out) approach. 7.3.7.1 Filling of the Data Buffer The write operation to the data buffer starts and stops as per the settings in the DATA_BUFFER_OPMODE register. The DATA_BUFFER_STATUS register provides the number of entries filled in the data buffer and this register can be read during an active sequence to get the current status of the data buffer. The time between two consecutive conversions is set by the nCLK register and Equation 3 provides the relationship for time between two consecutive conversions of the same channel and nCLK parameter. tcc = k x nCLK x OscillatorTimePeriod where • tcc is time between two consecutive conversions of same channel, tcc = k × tcycle . • k is number of channels enabled in the device sequence. • nCLK is number of clocks used by device for one conversion cycle. • Oscillator Timer Period is tLPO or tHSO depending on OSC_SEL value . Refer to the Specifications for tLPO or tHSO . (3) The format of the 16-bit contents of each entry in the data buffer are set by programming the DATA_OUT_CFG register. The DATA_OUT_CFG register enables the Channel ID and DATA_VALID flag in data buffer. Channel ID represents the channel number for the data entry in the data buffer. DATA_VALID is set to zero in either of the following conditions: |
Similar Part No. - ADS7142_17 |
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Similar Description - ADS7142_17 |
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