Sample

A

Sample

A+1

1

2

3

0

Data Output for Sample A-1

0

0

SCLK

SDO

CS

15

16

17

18

0

21

ADS7054

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SBAS859 – DECEMBER 2017

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Device Functional Modes (continued)

8.4.2 CNV State

In the CNV state, the device uses the external clock to convert the sampled analog input signal to an equivalent

digital code as per the transfer function illustrated in Figure 35. The conversion process requires a minimum of

18 SCLK falling edges to be provided within the frame. After the end of conversion process, the device

automatically moves from the CNV state to the ACQ state. For acquisition of the next sample, a minimum time of

Figure 37 shows a detailed timing diagram for the serial interface. In the first serial transfer frame after power-up,

the device provides the first data as all zeros. In any frame, the clocks provided on the SCLK pin are also used to

transfer the output data for the previous conversion. A leading 0 is output on the SDO pin on the CS falling edge.

The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge after the first

SCLK falling edge. Subsequent output bits are launched on the subsequent rising edges provided on SCLK.

When all 14 output bits are shifted out, the device outputs 0's on the subsequent SCLK rising edges. The device

If the device is provided with less than 18 SCLK falling edges in the present serial transfer frame, the device

provides an invalid conversion result in the next serial transfer frame.

Figure 37. Serial Interface Timing Diagram