First

Sample

Next

Sample

1

2

3

24

0

0

0

Data Output for First Sample

0

0

4

0

SCLK

SDO

CS

22

ADS7047

SBAS819 – DECEMBER 2017

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Copyright © 2017, Texas Instruments Incorporated

Device Functional Modes (continued)

(1)

In addition to the timing specifications of Figure 38 and Table 3, the timing specifications described in Figure 2 and the Timing

Requirements table are also applicable for offset calibration on power-up.

8.4.3 OFFCAL State

In the offset calibration (OFFCAL) state, the sampling capacitors are disconnected from the analog input pins

(AINP and AINM) and the device calibrates and corrects for any internal offset errors. The offset calibration is

effective for all subsequent conversions until the device is powered off. An offset calibration cycle is

recommended at power-up and whenever there is a significant change in the operating conditions for the device

(such as in the AVDD voltage and operating temperature).

The host controller must provide a serial transfer frame as described in Figure 38 or in Figure 39 to enter the

OFFCAL state.

8.4.3.1 Offset Calibration on Power-Up

On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL state. The device

provided.

If the host controller starts the offset calibration process but then pulls the CS pin high before providing 24

SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 38 and

Table 3 provide the timing for offset calibration on power-up.

Figure 38. Timing for Offset Calibration on Power-Up

MIN

TYP

MAX

UNIT

Cycle time for offset calibration on power-up

ns

Acquisition time

80

ns

Frequency of SCLK

60

MHz