ADC12020CIVYSLASHNOPB datasheet(3/30 Pages) TI1

Part #	ADC12020CIVY/NOPB

Description	12-Bit, 20 MSPS, 185 mW A/D Converter with Internal Sample-and-Hold

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AGND

ADC12020

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SNAS186B – APRIL 2003 – REVISED MARCH 2013

Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

Non-Inverting analog signal Input. With a 2.0V reference voltage, the

2

VIN+

differential input signal level is 2.0 VP-P centered on VCM.

Inverting analog signal Input. With a 2.0V reference voltage the ground-

referenced input signal level is 2.0 VP-P centered on VCM. This pin may be

3

VIN−

connected to VCM for single-ended operation, but a differential input signal

is required for best performance.

Reference input. This pin should be bypassed to AGND with a 0.1 µF

1

VREF

monolithic capacitor. VREF is 2.0V nominal and should be between 1.0V to

2.2V.

31

VRP

32

VRM

These pins are high impedance reference bypass pins. Connect a 0.1 µF

capacitor from each of these pins to AGND. DO NOT LOAD these pins.

30

VRN

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 100 kHz to 30

10

CLK

MHz (typical) with specified performance at 20 MHz. The input is sampled

on the rising edge of this input.

OE is the output enable pin that, when low, enables the TRI-STATE™ data

11

OE

output pins. When this pin is high, the outputs are in a high impedance

state.

PD is the Power Down input pin. When high, this input puts the converter

into the power down mode. When this pin is low, the converter is in the

8

PD

active mode.

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ADC12020CIVY/NOPB Datasheet(PDF) 3 Page - Texas Instruments

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