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ADC12DJ2700 Datasheet(PDF) 57 Page - Texas Instruments |
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ADC12DJ2700 Datasheet(HTML) 57 Page - Texas Instruments |
57 / 146 page 57 ADC12DJ2700 www.ti.com SLVSEH9 – JANUARY 2018 Product Folder Links: ADC12DJ2700 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 7.3.7.4.1 SerDes Pre-Emphasis The ADC12DJ2700 high-speed output drivers can pre-equalize the transmitted data stream by using pre- emphasis in order to compensate for the low-pass response of the transmission channel. Configurable pre- emphasis settings allow the output drive waveform to be optimized for different PCB materials and signal transmission distances. The pre-emphasis setting is adjusted through the serializer pre-emphasis setting SER_PE (in the serializer pre-emphasis control register). Higher values increase the pre-emphasis to compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. Adjust the pre-emphasis setting to optimize the eye-opening for the specific hardware configuration and line rates needed. 7.3.7.5 JESD204B Enable The JESD204B interface must be disabled through JESD_EN (in the JESD204B enable register) while any of the other JESD204B parameters are being changed. When JESD_EN is set to 0 the block is held in reset and the serializers are powered down. The clocks for this section are also gated off to further save power. When the parameters are set as desired, the JESD204B block can be enabled (JESD_EN is set to 1). 7.3.7.6 Multi-Device Synchronization and Deterministic Latency JESD204B subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices achieve the same deterministic latency then they can be considered synchronized. This latency must be achieved from system startup to startup to be deterministic. There are two key requirements to achieve deterministic latency. The first is proper capture of SYSREF for which the ADC12DJ2700 provides a number of features to simplify this requirement at giga-sample clock rates (see the SYSREF Capture for Multi-Device Synchronization and Deterministic Latency section for more information). The second requirement is to choose a proper elastic buffer release point in the receiver. Because the ADC12DJ2700 is an ADC, the ADC12DJ2700 is the transmitter (TX) in the JESD204B link and the logic device is the receiver (RX). The elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency variation of one LMFC period. Choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an LMFC edge, and the total expected delay variation for all devices. With this information the region of invalid release points within the LMFC period can be defined, which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must ensure that the data for all lanes arrives at all devices before the release point occurs. Figure 82 illustrates a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is shown. The second ADC has a longer routing distance (tPCB) and results in a longer link delay. First, the invalid region of the LMFC period is marked off as determined by the data arrival times for all devices. Then, the release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate number of frame clocks from the LMFC edge so that the release point occurs within the valid region of the LMFC cycle. In the case of Figure 82, the LMFC edge (RBD = 0) is a good choice for the release point because there is sufficient margin on each side of the valid region. |
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