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ADC12DJ2700 Datasheet(PDF) 35 Page - Texas Instruments |
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ADC12DJ2700 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 146 page  Sample Number 1600 1700 1800 1900 2000 2100 2200 2300 2400 0 100 200 300 400 500 D128 -0.35V Differential Sample Number 0 1000 2000 3000 4000 5000 6000 7000 8000 0 512 1024 1536 2048 2560 3072 3584 4096 Zoomed Area in Following Plot D127 +0.35 V Differential -0.35 V Differential 0 V Differential Sample Number 0 5000 10000 15000 20000 25000 30000 35000 0 500 1000 1500 2000 2500 3000 3500 4000 Zoomed Area in Following Plot D125 Sample Number 14800 15200 15600 16000 16400 1400 1600 1800 2000 2200 D126 JMODE 0 2 4 6 8 10 12 14 16 18 2.5 2.75 3 3.25 3.5 3.75 4 D033 FG Calibration BG Calibration LPBG Calibration JMODE 0 2 4 6 8 10 12 14 16 18 0 0.25 0.5 0.75 1 1.25 1.5 D122 IA19 IA11 ID11 35 ADC12DJ2700 www.ti.com SLVSEH9 – JANUARY 2018 Product Folder Links: ADC12DJ2700 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Typical Characteristics (continued) typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered, 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs (1) These curves are taken at a clock frequency higher than the rated maximum clock frequency but are representative of results at the rated maximum clock frequency. fIN = 2400 MHz, fCLK = 2700 MHz, BG calibration Figure 58. Supply Current vs JMODE fIN = 2400 MHz, fCLK = 2700 MHz Figure 59. Power Consumption vs JMODE JMODE0, fCLK = 3200 MHz, fIN = 3199.9 MHz Figure 60. Background Calibration Core Transition (AC Signal) (1) JMODE0, fCLK = 3200 MHz, fIN = 3199.9 MHz Figure 61. Background Calibration Core Transition (AC Signal Zoomed)(1) JMODE0, fCLK = 3200 MHz, DC input Figure 62. Background Calibration Core Transition (DC Signal)(1) JMODE0, fCLK = 3200 MHz, DC input Figure 63. Background Calibration Core Transition (DC Signal Zoomed)(1) |
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