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ZL50400GDC Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
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ZL50400GDC Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
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3 / 124 page  ZL50400 Data Sheet 3 Zarlink Semiconductor Inc. Description The ZL50400 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100 Mbps, and a CPU interface for lightly managed and unmanaged switch applications. The chip supports up to 4 K MAC addresses and port-based Virtual LANs (VLANs). With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50400 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50400 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50400 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50400 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50400 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50400 is fabricated using 0.18 micron technology. The ZL50400 is packaged in a 208-pin Ball Grid Array package. |
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