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VG36648041DTL-6 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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4 / 69 page Document :1G5-0177 Rev.2 Page 4 VIS VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM Pin Function Symbol Input Function CLK Input Maste Clock: Other inputs signals are referenecd to the CLK rising edge CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER- DOWN (row ACTIVE in any bank). /CS Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the com- mand decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. /RAS, /CAS, /WE Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. A0 - A13 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca- tion out of the memory array in the respective bank. The row address is specified by A0-A11. The column address is specified by A0-A9 (X4) / A0-A8 (X8) / A0-A7 (X16) BA0,BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. DQM, UDQM , LDQM Input Address Inputs: Provide the row address for ACTIVE commands (row address A0- A10), and the column address and AUTO PRECHARGE bit for READ/WRITE com- mands (column address A0-A7 with A10 defining AUTO PRECHARGE), to select one location out of the memory array in the respective bank. DQ0 - DQ15 I/O Data Input / Output: Data bus VDD, VSS Supply Power Supply for the memory array and peripheral circuitry VDDQ, VSSQ Supply Power Supply are supplied to the output buffers only |
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