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TC58DVM82A1FT00 Datasheet(PDF) 6 Page - Toshiba Semiconductor |
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TC58DVM82A1FT00 Datasheet(HTML) 6 Page - Toshiba Semiconductor |
6 / 34 page TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 6/34 Note: (1) CE High to Ready time depends on the pull-up resistor tied to the BY / RY pin. (Refer to Application Note (9) toward the end of this document.) (2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30 ns, BY / RY signal stays Ready. PROGRAMMING AND ERASING CHARACTERISTICS (Ta =0° to 70°C, VCC 2.7 V to 3.6 V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tPROG Programming Time 200 1000 s N Number of Programming Cycles on Same Page 3 (1) tBERASE Block Erasing Time 2 10 ms (1): Refer to Application Note (12) toward the end of this document. : 0 to 30 ns Busy signal is not output. A CE RE tCEH 100 ns * 525 Busy BY / RY *: VIH or VIL A 526 527 |
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