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STV3550 Datasheet(PDF) 3 Page - STMicroelectronics

Part # STV3550
Description  LCD and Matrix Display TV Processor
Download  144 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STV3550 Datasheet(HTML) 3 Page - STMicroelectronics

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4.4.1
Background Color Plane .......................................................................................................................54
4.4.2
Video Plane ..........................................................................................................................................54
4.4.3
Cursor Plane .........................................................................................................................................54
4.4.4
Graphics Plane .....................................................................................................................................54
Chapter 5
Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.1
Color Space Adaptor (CSA) and Interpolator ..................................................................... 56
5.1.1
Main Features .......................................................................................................................................56
5.1.2
General Description ..............................................................................................................................56
5.1.3
Up-sampling .........................................................................................................................................56
5.1.4
GFX_ACTIVE Signal ............................................................................................................................57
5.2
Gamma Correction ............................................................................................................. 59
5.3
Perfect Color Engine .......................................................................................................... 59
5.4
Digital Video Output Stage ................................................................................................. 59
5.4.1
Introduction ...........................................................................................................................................59
5.4.2
Vsync Output Capability .......................................................................................................................60
5.4.3
Hsync Output Capability .......................................................................................................................60
5.4.4
Csync Output Capability .......................................................................................................................60
5.4.5
RGB Output ..........................................................................................................................................60
5.4.6
Data Enable Output ..............................................................................................................................64
5.4.7
Data Clock Output ................................................................................................................................65
5.4.8
Pad Control ...........................................................................................................................................65
5.4.9
Register ................................................................................................................................................65
Chapter 6
CPU and System Management Functional Description . . . . . . . . . . . . . . . . . .66
6.1
ST20 C2C200 CPU Core ................................................................................................... 66
6.1.1
General Information ..............................................................................................................................66
6.1.2
Main Features .......................................................................................................................................66
6.2
ST Bus Interconnect Overview ........................................................................................... 66
6.3
STV3550 Memory Interface ............................................................................................... 66
6.3.1
Memory Devices ...................................................................................................................................66
6.3.2
Configuring the STV3550 Memory Interface during Boot .....................................................................67
6.3.3
Address Format ....................................................................................................................................67
6.3.4
Control Registers ..................................................................................................................................67
6.3.5
Memory Configurations ........................................................................................................................68
6.3.6
Clock Management and Timing Issues .................................................................................................68
6.3.7
STV3550 Memory Interfaces ................................................................................................................68
6.3.8
STV3550 Memory Interface Capabilities Regarding Flash Device .......................................................69
6.3.9
STV3550 Memory Interface Capabilities Regarding SDRAM Device ...................................................71
6.3.10
SDRAM Low Power Mode ....................................................................................................................75
6.3.11
Memory Configurations ........................................................................................................................76
6.3.12
STV3550 External and Internal Memory Mapping ................................................................................81
6.4
Reset Strategy ................................................................................................................... 81


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